For a long time, people have attempted to combine ESD performance and analog performance in a single circuit. However, it is not a straightforward task to match the ESD robustness with the analog performance, in particular RF performance. ESD elements are known to be inter alia large and frequency-dependent, which conflicts with the meticulous selection of the analog elements.
Roughly speaking, one can distinguish two design approaches when adding ESD functionality to an analog circuit: co-design and plug&play design. As the name indicates, in the plug&play design approach one inserts the designed ESD element, given the required ESD performance, as a whole in the analog circuit. The ESD element is then a compact element that is inserted where needed, typically as close as possible to the input/output pads. When ESD and analog performance is to be combined, it is important how the ESD parameters are selected. In the plug&play approach, one first optimizes the analog performance, and then determines the ESD elements and their layout with the aim to minimize the impact of ESD performance on analog performance. In this independent or successive design approach, ESD elements and analog elements are to a large extent independently developed, be it that the selection of ESD elements is subject to the analog performance. This is the most classical approach and is most often applied in digital design.
In the co-design or simultaneous approach, ESD elements are determined in view of their analog performance and analog elements are selected in view of their ESD performance. Hence, by determining the parameters of a circuit element, both the ESD and analog characteristics of this circuit element are taken into account. However, by taking the ESD protection into the analog design space, additional challenges are introduced to the freedom of the analog designer who previously only was concerned and knowledgeable about analog performance. When ESD and analog performance are to be matched, it is important how the ESD and RF parameters are selected.
Whether or not the ESD elements are selected with minimal impact on the analog parameters, i.e., the plug&play approach, or as part of the analog design, i.e., the co-design approach, one can still select how the ESD elements are inserted in the analog circuit. In the distributed approach, instead of inserting the compact ESD element at a single location in the analog circuit, one will distribute the ESD element over the whole of the analog circuit. In the distributed design, the ESD element is split or “distributed” over the analog circuit. An example of such distributed design is given by U.S. Pat. No. 5,969,929, where the ESD elements are distributed over the transmission line. The effective impedance of the distributed ESD elements and of the transmission line protected by the ESD elements is defined to match the impedance of external elements.
As a further example, U.S. Pat. No. 6,433,985 discloses an ESD protection network that prevents high voltage oxide stress. Due to device scaling, the dielectrics used in semiconductor processing become thinner and the effective electrical fields applied over these dielectrics will increase. In order to protect, for example, the gate dielectric of a transistor, from ESD events, such as overvoltage, at frequencies below the operational frequency of the circuit, a capacitor is inserted in the ESD network. This capacitor is designed to propagate signals at operational frequency, but to block or at least delay signals with a lower the operational frequency. The first ESD elements are designed to discharge the ESD current, while the second ESD elements will see a reduced signal due to the blocking capacitor. These second ESD elements can be made physically smaller, for example, by a factor of approximately three. The voltage level experienced by the gate dielectric during an ESD event is reduced by placing a blocking capacitor between the gate dielectric and the possible source of ESD event. All signals having a frequency equal to or higher then the operational frequency can pass. This design can be considered as a plug&play—independent design: the ESD element is added as whole to the input of the receiver, while the capacitance value is selected to have operational signals pass.